한빛출판네트워크

175 struct seq_operations cpuinfo_op = {
176   .start  = c_start,
177   .next = c_next,
178   .stop = c_stop,
179   .show = show_cpuinfo,
180 };

 75   struct cpuinfo_x86 *c = v;
 76   int i, n = c - cpu_data;
 77   int fpu_exception;
 78
 79 #ifdef CONFIG_SMP
 80   if (!cpu_online(n))
 81     return 0;
 82 #endif
 83   seq_printf(m, "processort: %dn"
 84     "vendor_idt: %sn"
 85     "cpu familyt: %dn"
 86     "modeltt: %dn"
 87     "model namet: %sn",
 88     n,
 89     c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
 90     c->x86,
 91     c->x86_model,
 92     c->x86_model_id[0] ? c->x86_model_id : "unknown");
 93
 94   if (c->x86_mask || c->cpuid_level >= 0)
 95     seq_printf(m, "steppingt: %dn", c->x86_mask);
 96   else
 97     seq_printf(m, "steppingt: unknownn");
 98
 99   if ( cpu_has(c, X86_FEATURE_TSC) ) {
100     unsigned int freq = cpufreq_quick_get(n);
101     if (!freq)
102       freq = cpu_khz;
103     seq_printf(m, "cpu MHztt: %u.%03un",
104       freq / 1000, (freq % 1000));
105   }

#define current_cpu_data cpu_data[smp_processor_id()]

105 #ifdef CONFIG_SMP
106 extern struct cpuinfo_x86 cpu_data[];
107 #define current_cpu_data cpu_data[smp_processor_id()]
108 #else
109 #define cpu_data (&boot_cpu_data)
110 #define current_cpu_data boot_cpu_data
111 #endif

107   /* Cache size */
108   if (c->x86_cache_size >= 0)
109     seq_printf(m, "cache sizet: %d KBn", c->x86_cache_size);
110 #ifdef CONFIG_X86_HT
111   if (c->x86_max_cores * smp_num_siblings > 1) {
112     seq_printf(m, "physical idt: %dn", c->phys_proc_id);
113     seq_printf(m, "siblingst: %dn", cpus_weight(cpu_core_map[n]));
114     seq_printf(m, "core idtt: %dn", c->cpu_core_id);
115     seq_printf(m, "cpu corest: %dn", c->booted_cores);
116   }
117 #endif

155   seq_printf(m, "nbogomipst: %lu.%02lun",
156          c->loops_per_jiffy/(500000/HZ),
157          (c->loops_per_jiffy/(5000/HZ)) % 100);
158   seq_printf(m, "clflush sizet: %unn", c->x86_clflush_size);
159

 49 struct cpuinfo_x86 {
 50   __u8  x86;    /* CPU family */
 51   __u8  x86_vendor; /* CPU vendor */
 52   __u8  x86_model;
 53   __u8  x86_mask;
 54   char  wp_works_ok;  /* It doesn"t on 386"s */
 55   char  hlt_works_ok; /* Problems on some 486Dx4"s and old 386"s */
 56   char  hard_math;
 57   char  rfu;
 58         int cpuid_level;  /* Maximum supported CPUID level, -1=no CPUID */
 59   unsigned long x86_capability[NCAPINTS];
 60   char  x86_vendor_id[16];
 61   char  x86_model_id[64];
 62   int   x86_cache_size;  /* in KB - valid for CPUS which support this
 63             call  */
 64   int   x86_cache_alignment;  /* In bytes */
 65   char  fdiv_bug;
 66   char  f00f_bug;
 67   char  coma_bug;
 68   char  pad0;
 69   int x86_power;
 70   unsigned long loops_per_jiffy;
 71 #ifdef CONFIG_SMP
 72   cpumask_t llc_shared_map; /* cpus sharing the last level cache */
 73 #endif
 74   unsigned char x86_max_cores;  /* cpuid returned max cores value */
 75   unsigned char apicid;
 76   unsigned short x86_clflush_size;
 77 #ifdef CONFIG_SMP
 78   unsigned char booted_cores; /* number of cores as seen by OS */
 79   __u8 phys_proc_id;    /* Physical processor id. */
 80   __u8 cpu_core_id;     /* Core id */
 81 #endif
 82 } __attribute__((__aligned__(SMP_CACHE_BYTES)));

 
 79 /* cpu data as detected by the assembly code in head.S */
 80 struct cpuinfo_x86 new_cpu_data __cpuinitdata = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
 81 /* common cpu data for all cpus */
 82 struct cpuinfo_x86 boot_cpu_data __read_mostly = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
 83 EXPORT_SYMBOL(boot_cpu_data);

CPU0: Intel(R) Core(TM)2 CPU         T7200  @ 2.00GHz stepping 08